1. Field of the Invention
The present invention relates to a micro-semiconductor device and an integrated circuit using the same. The present invention also relates to a process for producing a micro-semiconductor device.
2. Description of the Prior Art
So-called MOS (metal-oxide-semiconductor) and MIS (metal-insulator-semiconductor) field effect transistors (collectively referred to hereinafter as MISFETs) are the essential devices for integrated circuits (ICs), large scale integrated circuits (LSIs), and very-large scale integrated circuits (VLSIs). More advanced MISFETs are now developed with progress in the development of finer and faster devices.
An LDD(lightly doped drain)-type MISFET is known as the most advanced MISFET at the present. A schematically drawn structure of this device is given in FIG. 1. A MISFET of this structure is characterized by that the impurity region provided on the substrate, such as the source and the drain, has a continuously changing concentration, since there is no large electric field generated at the phase boundary between the impurity region and the channel region. Referring to FIG. 1, for example, areas changed in the conductive type are established, from a source electrode 107 to an n.sup.+ -type first source 102, then to an n.sup.- -type second source 103, a p.sup.- -type channel 108, followed by an n.sup.- -type second drain 104, an n.sup.- -type first drain 105, and finally to a drain electrode 106. Thus, because of a moderate gradient in the electric field at the boundary between the channel region and the impurity region, defects due to over-acceleration of the carriers at this region are less produced on the semiconductors and the gate insulator films. The LDD-type MISFETs are therefore endurable for use over a long period of time.
In a typical LDD-type MISFET as illustrated in FIG. 1, however, several problems arise with increasing fineness of the devices. Representatively, there can be mentioned an overlap of the impurity region and the gate electrode, and a concentration of the electric field between the impurity regions right below the gate insulator film. The former concerns the process. In general, the impurity region is established by ion-implantation, i.e., by bombarding the substrate with impurity ions in a self-consistent manner using the gate electrode as the mask. Ideally, there should be no overlap between the gate electrode and the impurity region, however, in practice, the impurity ions go beyond the desired region to the portion under the gate electrode. The reason for such overlapping is considered mainly due to the incident impurity ion beams which undergo a secondary scattering upon irradiation on the crystal lattices of the semiconductor substrate. This phenomena is more enhanced with increasing energy of the incident ion beam energy, and more pronounced with relative decrease in the gate width, i.e., the channel length. An overlap of the impurity region and the electrode impairs the speed of the MISFET due to the increased parasitic capacity between the gate electrode and the impurity region.
The latter of the aforementioned problems is also a serious problem in the case of a typical LDD-type MISFET. Referring to the MISFET as shown in FIG. 1, which comprises an impurity region of the structure as illustrated, the electric field become most concentrated between the points A and B at the ends of the second source region and of the second drain regions, respectively, upon application of a voltage between the source and the drain. Accordingly, the most accelerated carriers run between the two points, A and B; hence. the gate insulator films are liable to be damaged since those points are located right under them. The gate insulator film thus damaged by the accelerated carriers generates charge trap centers, and, in an extreme case, the gate electrode completely loses the ability to control the carrier passing through the channel region.
As a measure to overcome the aforementioned problems, an LDD-type MISFET as shown in FIG. 2 (a) has been proposed. The very difference between this MISFET and the conventional LDD-type MISFET of the structure given in FIG. 1 is that the points A and B, which are the end points of the second source region and the second drain region, respectively, are located remotely from the gate insulator films. Thus, the gate insulator films are less damaged by the concentration of the electric field to these two points. Furthermore, because of the electrode established distant from the impurity region, as it can be seen clearly from FIG. 2(a), the parasitic capacity can be reduced despite of the overlapping of the electrode and the impurity region.
The LDD-type MISFETs of this structure can be fabricated by bombarding impurity ions from an oblique direction with respect to the surface. However, an MISFET with a channel length of 0.5 .mu.m or less cannot be expected with a high yield because of the difficulty encountered in its fabrication process. More specifically, such structures can be fabricated with good reproducibility only when the accelerating energy of the impurity ions are controlled with high precision and when a highly ordered ion source is available. If those requirements are not sufficiently achieved at the fabrication process, the oblique incident ion beams enter into an unexpectedly deep region to result in a fused impurity region, as is shown in FIG. 2(b). This phenomena become more pronounced with minimizing the channel length.
In conclusion, it is industrially unfeasible to adapt the conventional LDD-type MISFETs, inclusive of the modified type as shown in FIG. 2, to MISFETs having a channel length of 0.5 .mu.m or less, particularly to the so-called quarter-micrometer MISFETs having a channel length of 0.3 .mu.m or less.